Sandy Bridge Chipset Shipments Halted Due To Bug

J. Dzhugashvili writes "Early adopters of Intel's new Sandy Bridge processors, beware. Intel has discovered a flaw in the 6-series chipsets that accompany the new processors. The flaw causes Serial ATA performance to 'degrade over time' in 'some cases.' Although Intel claims 'relatively few' customers are affected, it has stopped shipments of these chipsets and started making a revised version of the silicon, which won't be ready until late February. Intel expects to lose $300 million in revenue because of the problem, and it's bracing for repair and replacement costs of $700 million."

Some additional information

[dc29A]

Apparently the problem [notebookreview.com] is with SATA ports 2-5, at least for mobile motherboards. Every desktop board is affected.

Re:First Stalin, now this. You Georgians, I swear.

[Chemicles]

Or, they could be actual quotes from the company's actual press release [intel.com].

Re:Why Sandy Bridge ?

[Anonymous Showered]

Sandy Bridge is the successor to Nehalem. It uses less power and is more efficient.

The current P67 boards (LGA 1155) are for the mainstream market, e.g. Best Buy, Futureshop, Fry's, Staples, etc. They're basically "high-end' for the middle-class.

Wait until LGA 2011 comes out (successor to 1366). You'll be thinking of switching then. :)

Re:Intel caught this one first?

[Ecuador]

According to Anand's coverage, Intel said that they started getting customer complaints after they had shipped about 100k units, and their engineers managed to duplicate the problem early last week, the cause of which they figured out in a couple of days.

Source : http://www.anandtech.com/show/4142/intel-discovers-bug-in-6series-chipset-begins-recall [anandtech.com]

Re:Why Sandy Bridge ?

[PitaBred]

Yes. Sandy Bridge i7-2600K CPUs are approaching the speeds of the i7-980X, while costing 1/3rd as much. You can build an insanely fast machine for under $1000 with Sandy Bridge, including graphics card.

Re:Why Sandy Bridge ?

[DoofusOfDeath]

What's the big appeal of Sandy Bridge anyway ?

For some of us (including me), the big deal is that Sandy Bridge adds a new set of instructions called "AVX" intstructions, which let us do more floating-point operations at the same time. For some scientific apps this can nearly double the performance of the overall app.

Re:Why Sandy Bridge ?

[Theovon]

There are a number of really good articles on the advances in Sandy Bridge. For instance:

http://www.realworldtech.com/page.cfm?ArticleID=RWT091810191937
http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed

To summarize some of the things I remember off the top of my head:

The design is basically area-equivalent to the Nehalem designs, but they've made certain structures more space efficient to make room to enlarge others. For instance, they've made the branch predictor use fewer bits for the same prediction accuracy. This and other improvements have allowed them to increase critical structures that affect things like the instruction window size. The instruction window pertains to the number of decoded but not executed instructions out-standing. A larger instruction window allows you to (a) find more instruction-level parallelism because you're more likely to find independent instructions that can be executed simultaneously, and (b) absorb the effect of some high latency operations, like L2 cache misses -- you can effectively hide much of the latency by continuing to look for and perform unrelated work during the stall. In Nehalem and before, they had a structure that unified the reservation station, register file, and reorder buffer. Logically, this makes sense, but it also makes that area very power hungry, and you can never turn it off. In Sandy Bridge, they've split those structures, so they can be clock-gated separately. Also, instead of accumulating dependency results in the reservation station, they're stored in a single centralized physical register file, and pointers are held in the RS. This saves a lot of space, since now instructions traveling around the processor just need to carry the pointer. (This does add some latency and writing required to fetch those results from the RF when they're finally needed.)

It's explicitly stated that Sandy Bridge is not a major revolution in processor design. Compared to Nehalem, you might think of it representing a large collection of efficiency improvements that work together to make a processor that is faster (clock for clock efficiency) and more power efficient.

Many of these improvements lead to the larger instruction window. IMHO, this is a critical improvement. A Sun engineer once described modern processing as being a race between last-level cache misses. You have an L2 miss, and you quickly run out of work to do, and the processor stalls until that out-standing read arrives. Meanwhile, you've accumulated a hundred cycles or so of pending work, which gets blasted through, and execution continues perhaps a little while until you have another L2 miss. Processors like Nehalem can execute four or more instructions per cycle (peak), but the effective AVERAGE instructions per clock is less than 1. These high-latency L2 misses are primarily responsible for that. Besides adding on-die memory controllers, which reduces the latency, Sandy Bridge lengthens the instruction window so as to absorb more of that latency, so that stall time is less.

Re:Over time?

[ShnowDoggie]

The problem in the chipset was traced back to a transistor in the 3Gbps PLL clocking tree. The aforementioned transistor has a very thin gate oxide, which allows you to turn it on with a very low voltage. Unfortunately in this case Intel biased the transistor with too high of a voltage, resulting in higher than expected leakage current. Depending on the physical characteristics of the transistor the leakage current here can increase over time which can ultimately result in this failure on the 3Gbps ports.

~http://www.anandtech.com/show/4143/the-source-of-intels-cougar-point-sata-bug